1. Field
One or more embodiments of the present invention relate to a method of controlling a cache memory and an apparatus for performing the method.
2. Description of the Related Art
A coding or decoding technology of full high definition (FHD) or ultra high definition (UD) images is increasingly in demand as image-related technology improves. Accordingly, a technology of a processor handling the image in more detail is required. For example, when the image is processed by a method such as motion compensation (MC), a situation may happen where the processor repetitively requests transmission of previously-used data which is stored in a main memory. Then, previously transmitted data is transmitted again to the processor and the overhead due to accessing the main memory highly increases.
A cache memory is located between the processor and the main memory, and operates much faster than the main memory even though the size of the cache memory is smaller than that of the main memory. Thus, when a data requested for transmission exists in the cache memory, use of the cache memory may increase data processing speed since the data may be used by reading out the cache memory without accessing the main memory.